Flip Chip Die-to-Wafer Bonding Review: Gaps to High Volume Manufacturing

Authors

  • Mario Di Cino Department of Electrical and Computer Engineering, University of Idaho, Moscow, Idaho, 83844, USA
  • Feng Li Department of Electrical and Computer Engineering, University of Idaho, Moscow, Idaho, 83844, USA

DOI:

https://doi.org/10.30564/ssid.v4i1.4474

Abstract

Flip chip die-to-wafer bonding faces challenges for industry adoption due to a variety of technical gaps or process integration factors that are not fully developed to high volume manufacturing (HVM) maturity. In this paper,flip-chip and wire bonding are compared, then flip-chip bonding techniques are compared to examine advantages for scaling and speed. Specific recent 3-year trends in flip-chip die-to-wafer bonding are reviewed to address the key gaps and challenges to HVM adoption. Finally, some thoughts on the care needed by the packaging technology for successful HVM introduction are reviewed.

Keywords:

Flip chip, Die-to-Wafer (D2W), Chip-to-Wafer (C2W), Chip-scale packaging (CSP), High volume manufacturing (HVM), Known good die (KGD), Through silicon via (TSV), Reliability

References

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How to Cite

Di Cino, M., & Li, F. (2022). Flip Chip Die-to-Wafer Bonding Review: Gaps to High Volume Manufacturing. Semiconductor Science and Information Devices, 4(1), 8–13. https://doi.org/10.30564/ssid.v4i1.4474

Issue

Vol. 4 , Iss. 1 (April 2022)

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